為了方便做筆記，從移位寄存器（Shift Registers）這章開始按章節(jié)做記錄。
1.? ?4-bit Shift Registers
題目：
Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.
- areset: Resets shift register to zero.
- load: Loads shift register with?data[3:0]?instead of shifting.
- ena: Shift right (q[3]?becomes zero,?q[0]?is shifted out and disappears).
- q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.
思路：
設計一個4位邏輯移位寄存器（右移），寄存器具有異步復位，同步加載和使能。
復位：寄存器置為0。
加載：加載data[3:0]到寄存器中。
使能：寄存器右移。
q：移位寄存器。
需要注意的是，題目要求當加載和使能同時為高電平時，優(yōu)先對數(shù)據(jù)進行加載。
代碼：文章來源地址http://www.zghlxwxcb.cn/news/detail-403654.html
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always@(posedge clk, posedge areset) begin
if(areset)
q<=0;
else if(load)
q <= data;
else if(ena) begin
q[0]<=q[1];
q[1]<=q[2];
q[2]<=q[3];
q[3]<=0;
// q <=q[3:1];
end
end
endmodule2.Left/right rotator
題目：
Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
- load: Loads shift register with?data[99:0]?instead of rotating.
- ena[1:0]: Chooses whether and which direction to rotate.
- 2'b01?rotates right by one bit
- 2'b10?rotates left by one bit
- 2'b00?and?2'b11?do not rotate.
- q: The contents of the rotator.
思路：?
顧名思義是一個可控制左移/右移的循環(huán)移位寄存器，同步加載。與題1不同的是，移位后的數(shù)據(jù)將會翻折到另一端而不是置0。
題中使能端ena[1:0]控制寄存器是否左移/右移。
代碼：
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always@(posedge clk) begin
if(load)
q <= data;
else begin
case(ena)
2'b01: q <= {q[0],q[99:1]};
2'b10: q <= {q[98:0],q[99]};
default: q <= q;
endcase
end
end
endmodule3.Left/right arithmetic shift by 1 0r 8
題目：
Build a 64-bit?arithmetic?shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by?amount.
An?arithmetic?right shift shifts in the sign bit of the number in the shift register (q[63]?in this case) instead of zero as done by a?logical?right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
There is no difference between logical and arithmetic?left?shifts.
- load: Loads shift register with?data[63:0]?instead of shifting.
- ena: Chooses whether to shift.
- amount: Chooses which direction and how much to shift.
- 2'b00: shift left by 1 bit.
- 2'b01: shift left by 8 bits.
- 2'b10: shift right by 1 bit.
- 2'b11: shift right by 8 bits.
- q: The contents of the shifter.
思路：?
本題要求設計一個可實現(xiàn)左移/右移功能的算數(shù)移位寄存器，與邏輯移位寄存器不同的地方在于，有符號數(shù)需要考慮算數(shù)右移。
對于無符號數(shù)，算數(shù)移位寄存器與邏輯移位寄存器實現(xiàn)方法一致。
對于有符號數(shù)，算數(shù)左移與邏輯左移一致，移位后補0；算數(shù)右移與邏輯右移不同，算數(shù)右移左側(cè)需補充符號位而非0。
代碼：
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always@(posedge clk) begin
if(load)
q <= data;
else if(ena)
begin
case(amount)
2'b00: q <= {q[62:0],1'b0};
2'b01: q <= {q[55:0],{8{1'b0}}};
2'b10: q <= {q[63],q[63:1]};
2'b11: q <= {{8{q[63]}},q[63:8]};
endcase
end
end
endmodule4.? ? 5bits LFSR
題目：
A?linear feedback shift register?is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).
The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.
思路：
題目提供了一個線性反饋移位寄存器的電路圖，這一個帶有若干個XOR門的移位寄存器，將帶有抽頭的位置與輸出位進行異或運算來產(chǎn)生下一個值。
代碼：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always@(posedge clk) begin
if(reset)
q <= 5'h1;
else begin
q[4] <= q[0]^0;
q[3] <= q[4];
q[2] <= q[3]^q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
endmodule官方解法：
module top_module(
input clk,
input reset,
output reg [4:0] q);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit positions that have taps.
// A logic synthesizer creates a circuit that behaves as if the code were
// executed sequentially, so later assignments override earlier ones.
// Combinational always block: Use blocking assignments.
always @(*) begin
q_next = q[4:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[4] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[2] = q[3] ^ q[0];
end
// This is just a set of DFFs. I chose to compute the connections between the
// DFFs above in its own combinational always block, but you can combine them if you wish.
// You'll get the same circuit either way.
// Edge-triggered always block: Use non-blocking assignments.
always @(posedge clk) begin
if (reset)
q <= 5'h1;
else
q <= q_next;
end
endmodule5.? ? ?3-bit LFSR
題目：
Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named?top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the?R?inputs to the?SW?switches, connect Clock to?KEY[0], and?L?to?KEY[1]. Connect the?Q?outputs to the red lights?LEDR.
?為題目所給的時序邏輯電路寫一段代碼。其中輸入R為SW，時鐘信號為KEY[0],選擇器判別信號為KEY[1],輸出Q為LEDR。
思路：
將時序和組合分別寫在兩個模塊內(nèi)，一個實現(xiàn)觸發(fā)器功能，一個實現(xiàn)選擇器功能。
代碼：
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
reg [2:0] temp;
always@(*) begin
temp[0] = KEY[1] ? SW[0] : LEDR[2];
temp[1] = KEY[1] ? SW[1] : LEDR[0];
temp[2] = KEY[1] ? SW[2] : (LEDR[2]^LEDR[1]);
end
always@(posedge KEY[0]) begin
LEDR[2] <= temp[2];
LEDR[1] <= temp[1];
LEDR[0] <= temp[0];
end
endmodule6. 32-bit LFSR
題目：
Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
This is long enough that you'd want to use vectors, not 32 instantiations of DFFs.
思路：
設計一個32位的LFSR，抽頭位置在32,22,2,1。與LFSR5思路一致，只是寄存器位數(shù)較大，因此題目提示我們不要實例化32個觸發(fā)器。
可以直接對Q（即qnext）進行移位運算，再對抽頭位置逐一進行修正。
代碼：
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] Q;
always@(*) begin
Q = {q[0],q[31:1]};
Q[21] = q[22]^q[0];
Q[1] = q[2]^q[0];
Q[0] = q[1]^q[0];
end
always@(posedge clk) begin
if(reset)
q <= 32'h1;
else
q <= Q;
end
endmodule7.Shift register（Exams/m2014 q4k）
題目：
Implement the following circuit:
?思路：
實現(xiàn)上述時序電路，包含4個DFF，1個輸入in，1個輸入out，所有觸發(fā)器具有相同輸入的時鐘信號以及同步復位信號resetn（低電平有效）。
考慮創(chuàng)建一個寄存器Q來存儲觸發(fā)器的輸出值。
代碼：
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg[3:1] Q;
always@(posedge clk) begin
if(!resetn) begin
Q <= 0;
out <=0;
end
else begin
Q[1] <= in;
Q[2] <= Q[1];
Q[3] <= Q[2];
out <= Q[3];
end
end
endmodule官方解法：
module top_module (
input clk,
input resetn,
input in,
output out
);
reg [3:0] sr;
// Create a shift register named sr. It shifts in "in".
always @(posedge clk) begin
if (~resetn) // Synchronous active-low reset
sr <= 0;
else
sr <= {sr[2:0], in};
end
assign out = sr[3]; // Output the final bit (sr[3])
endmodule
8.Shift register（Exams/2014 q4b）
題目：
Consider the?n-bit shift register circuit shown below:
Write a top-level Verilog module (named top_module) for the shift register, assuming that?n?= 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.
- Connect the?R?inputs to the?SW?switches,
- clk?to?KEY[0],
- E?to?KEY[1],
- L?to?KEY[2], and
- w?to?KEY[3].
- Connect the outputs to the red lights?LEDR[3:0].
(Reuse your MUXDFF from?exams/2014_q4a.)
思路：
題目給出了一個n-bit移位寄存器電路，要求我們按照該電路的模式設計一個4-bit移位寄存器。
題目要求實例化4個由“兩個選擇器+單個觸發(fā)器“”組成的MUXDFF來完成電路設計。
代碼：
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF u4(
.clk(KEY[0]),
.E (KEY[1]),
.R (SW[3]),
.L (KEY[2]),
.w (KEY[3]),
.Q (LEDR[3])
);
MUXDFF u3(
.clk(KEY[0]),
.E (KEY[1]),
.R (SW[2]),
.L (KEY[2]),
.w (LEDR[3]),
.Q (LEDR[2])
);
MUXDFF u2(
.clk(KEY[0]),
.E (KEY[1]),
.R (SW[1]),
.L (KEY[2]),
.w (LEDR[2]),
.Q (LEDR[1])
);
MUXDFF u1(
.clk(KEY[0]),
.E (KEY[1]),
.R (SW[0]),
.L (KEY[2]),
.w (LEDR[1]),
.Q (LEDR[0])
);
endmodule
module MUXDFF (
input clk,
input E,
input R,
input L,
input w,
output Q
);
wire t1,t2;
always@(*) begin
t1 = E ? w:Q;
t2 = L ? R:t1;
end
always@(posedge clk) begin
Q <= t2;
end
endmodule9.? ? ?3-input LUT（Exams/ece241 2013 q12）
題目：
In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.
First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called?S, which feeds the input of Q[0] (MSB is shifted in first). The?enable?input controls whether to shift. Then, extend the circuit to have 3 additional inputs?A,B,C?and an output?Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).
思路：
用8個觸發(fā)器和1個3輸入單輸出的選擇器設計一個3輸入的查找表。
觸發(fā)器輸出Q[7:0]可以用向量完成，這樣就不需要實例化8個D觸發(fā)器。
查找表部分，因為只是一個3-input的查找表，直接用case枚舉了所有可能，實際上在設計一個n-input的查找表時，代碼的第一個always塊部分應該直接用Z=Q[{A,B,C}]代替。文章來源：http://www.zghlxwxcb.cn/news/detail-403654.html
代碼：
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output Z );
reg [7:0] Q;
always@(*) begin
case({A,B,C})
3'b000: Z = Q[0];
3'b001: Z = Q[1];
3'b010: Z = Q[2];
3'b011: Z = Q[3];
3'b100: Z = Q[4];
3'b101: Z = Q[5];
3'b110: Z = Q[6];
3'b111: Z = Q[7];
endcase
end
always@(posedge clk) begin
if(enable)
Q <= {Q[6:0],S};
else
Q <= Q;
end
endmodule到了這里，關(guān)于HDLBits學習筆記——移位寄存器的文章就介紹完了。如果您還想了解更多內(nèi)容，請在右上角搜索TOY模板網(wǎng)以前的文章或繼續(xù)瀏覽下面的相關(guān)文章，希望大家以后多多支持TOY模板網(wǎng)！
