AXI4-Full Xilinx FPGA使用理解---信號定義理解

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一、AXI4

signal	dir	Xilinx	中文理解
ID類
AWID	M2S	Masters need only output the set of ID bits that it varies (if any) to indicate re-orderable transaction threads. Single-threaded master interfaces can omit this signal. Masters do not need to output the constant portion that comprises the Master ID, as this is appended by the AXI Interconnect.	當只有一個主接口時無需關(guān)心此接口，當有多個主接口時也可把它設(shè)置成一個固定值，當有多個主時這個也可設(shè)置成一個固定值，實際輸出給DDR的AWID由AXI Interconnect給出。
BID	S2M	See AWID for more information.	wirte response channel
ARID	M2S	Masters need only output the set of ID bits that it varies (if any) to indicate re-orderable transaction threads. Single-threaded master interfaces can omit this signal. Masters do not need to output the constant portion that comprises the “Master ID”, as this is appended by the AXI Interconnect.	使用方式同AWID
RID	M2S	See ARID for more information.	同ARID一致
region類
AWREGION	M2S	Can be implemented in Xilinx Endpoint slave IP. Not present on master IP. Generated by AXI Interconnect using corresponding address decoder range settings.	區(qū)域標識符，允許一個從設(shè)備的單個物理接口用作多個邏輯接口，一般設(shè)置為4‘b0000
ARREGION	M2S	Can be implemented in Xilinx Endpoint Slave IP. Not present on master IP. Generated by AXI Interconnect using corresponding address decoder range settings.	區(qū)域標識符，允許一個從設(shè)備的單個物理接口用作多個邏輯接口，一般設(shè)置為4‘b0000
lock類
AWLOCK	M2S	Exclusive access support not implemented in endpoint Xilinx IP. Infrastructure IP will pass exclusive access bit across a system.	這個信號在AXI3協(xié)議中用于鎖定從機占用總線，但在AXI4中取消了相關(guān)支持，僅留下一位信號用作指示為正常傳輸(1'b0)，還是獨有傳輸(1'b1),一般設(shè)置為1’b0
ARLOCK	M2S	Exclusive access support not implemented in Endpoint Xilinx IP. Infrastructure IP passes exclusive access bit across a system.	這個信號在AXI3協(xié)議中用于鎖定從機占用總線，但在AXI4中取消了相關(guān)支持，僅留下一位信號用作指示為正常傳輸(1'b0)，還是獨有傳輸(1'b1),一般設(shè)置為1’b0
CACH類
AWCACH	M2S	0011 value recommended. Xilinx IP generally ignores (as slaves) or generates (as masters) transactions as Normal, Non-cacheable, Modifiable, and Bufferable. Infrastructure IP will pass Cache bits across a system.	xilinx建議此值給0011也有一些資料建議此值給0010(不使用cache補使用buff)
ARCACH	M2S	0011 value recommended. Xilinx IP generally ignores (as slaves) or generates (as masters) transactions with Normal, Non-cacheable, Modifiable, and Bufferable. Infrastructure IP will pass Cache bits across a system.	xilinx建議此值給0011也有一些資料建議此值給0010(不使用cache補使用buff)
PROT(權(quán)限控制)
AWPROT	M2S	000 value recommended. Xilinx IP generally ignores (as slaves) or generates transactions (as masters) with Normal, Secure, and Data attributes. Infrastructure IP passes Protection bits across a system.
ARPROT	M2S	Xilinx IP generally ignore (as slaves) or generate transactions (as masters) with Normal, Secure, and Data attributes. Infrastructure IP passes Protection bits across a system. 000 value recommended.
QOS
AWQOS	M2S	Not implemented in Xilinx Endpoint IP. Infrastructure IP passes QoS bit across a system.	xilinx AXI4不支持設(shè)置為0
ARQOS	M2S	Not implemented in Xilinx Endpoint IP. Infrastructure IP passes QoS bit across a system	xilinx AXI4不支持設(shè)置為0
USER
AWUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP passes USER bits across a system.	xilinx AXI4不支持設(shè)置為0
WUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	xilinx AXI4不支持設(shè)置為0
BUSER	S2M	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	來自寫相應(yīng)通道， xilinx AXI4不支持。
ARUSER	M2S	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP passes USER bits across a system.	xilinx AXI4不支持設(shè)置為0
RUSER	S2M	Generally, not implemented in Xilinx endpoint IP. Infrastructure IP will pass USER bits across a system.	xilinx AXI4不支持
地址寫
AWADDR	M2S	Widths up to 64 bits. High-order bits outside the native address range of a slave are ignored (trimmed), by an endpoint slave, which could result in address aliasing within the slave.	寫地址。寫地址給出突發(fā)數(shù)據(jù)傳輸?shù)?u>第一個傳輸?shù)刂贰?/p>
AWLEN	M2S	Support bursts: ? Up to 256 beats for incrementing ( INCR ). ? 16 beats for WRAP .	突發(fā)長度。給出突發(fā)傳輸中準確的傳輸個數(shù)。支持INCR和WRAP傳輸模式。突發(fā)長度=awlen+1
AWSIZE	M2S	Transfer width 8 to 1024 bits supported. Use of narrow bursts where AWSIZE is less than the native data width is not recommended.	突發(fā)大小。這個信號用于確定突發(fā)傳輸中每個傳輸?shù)拇笮　?/p> 總線位寬=2^size Betyes(例如總線位寬為512bit，則AWSIZE為6),指示有效字節(jié)數(shù)，如果位寬為512bit,但有效位寬為32bit則此位填2
AWBURST	M2S	INCR and WRAP fully supported. FIXED bursts are not recommended. Conversions of FIXED bursts through AXI Interconnect infrastructure may have sub-optimal performance.	00:FIXED 01:INCR 10:WRAP 11:保留
AWVALID	M2S	Fully supported	主設(shè)備給出的地址和相關(guān)控制信號有效
AWREADY	S2M	Fully supported	從設(shè)備已準備好接收地址和相關(guān)的控制信號
數(shù)據(jù)寫
WDATA	M2S	Native width 32 to 1024 bits supported.	寫數(shù)據(jù)，32位到1024位寬
WSTRB	M2S	Fully supported.	寫字節(jié)選通，用于表示更新存儲器的字節(jié)通道，對于數(shù)據(jù)總線的每8位數(shù)據(jù)有一位寫選通信號。
WLAST	M2S	Fully supported.	寫最后一個數(shù)據(jù)指示信號。表示突發(fā)傳輸中的最后一個數(shù)據(jù)。
WVALID	M2S	Fully supported.	寫有效。為高指示數(shù)據(jù)有效。
WREADY	S2M	Fully supported.	寫準備。為高表示從設(shè)備空閑，準備接收數(shù)據(jù)；為低表示從設(shè)備忙
寫響應(yīng)
BRESP	S2M	Fully supported.	指示寫的結(jié)果 00:OKAY 正常訪問成功，還可以指示獨占訪問失敗。 01：EXOKAY指示獨占訪問的部分已成功。 10：SLVERR主機正常發(fā)送但是從機沒有正常接收。 11：DECERR主機沒找到從機
BVALID	S2M	Fully supported.	寫響應(yīng)有效。為高指示響應(yīng)數(shù)據(jù)有效。
BREADY	M2S	Fully supported.	寫響應(yīng)準備。為高表示主設(shè)備空閑，準備接收寫響應(yīng)；為低表示主設(shè)備忙。
讀地址
ARADDR	M2S	Widths up to 64 bits. High-order bits outside the native address range of a slave are ignored (trimmed) by an endpoint slave, which could result in address aliasing within the slave.	讀地址。讀地址給出突發(fā)數(shù)據(jù)傳輸?shù)牡谝粋€傳輸?shù)刂贰?/td>
ARLEN	M2S	Support bursts: ? Up to 256 beats for incrementing ( INCR ). ? 16 beats for WRAP .	突發(fā)長度。給出突發(fā)傳輸中準確的傳輸個數(shù)。支持INCR和WRAP傳輸模式。
ARSIZE	M2S	Transfer width 8 to 1024 bits supported. Use of narrow bursts where ARSIZE is less than the native data width is not recommended.	突發(fā)大小。這個信號用于確定突發(fā)傳輸中每個傳輸?shù)拇笮?。，定義和AWSIZE相同。
ARBURST	M2S	INCR and WRAP fully supported. FIXED bursts are not recommended. Conversions of FIXED bursts through AXI Interconnect infrastructure may have sub-optimal performance.	突發(fā)類型。該信息與突發(fā)大小信息一起，表示在突發(fā)過程中，地址如何應(yīng)用于每個傳輸。支持INCR和WRAP傳輸模式。
ARVALID	M2S	Fully supported.	讀地址有效信號。為高指示地址有效。
ARREADY	S2M	Fully supported.	讀地址準備信號。為高表示從設(shè)備空閑，準備接收地址；為低表示從設(shè)備忙。
讀數(shù)據(jù)
RDATA	S2M	Native width 32 to 1024 bits supported.	讀數(shù)據(jù)。32位到1024位寬
RRESP	S2M	Fully supported.	讀響應(yīng)。該信號表示讀狀態(tài)，可允許相應(yīng)的表示為OKAY\EXOKAY\SLVERR\DECERR。
RLAST	S2M	Fully supported.	讀最后一個數(shù)據(jù)指示信號。表示突發(fā)傳輸中的最后一個數(shù)據(jù)。
RVALID	S2M	Fully supported.	讀有效。為高指示數(shù)據(jù)有效。
RREADY	M2S	Fully supported.	讀準備。為高表示主設(shè)備空閑，準備接收數(shù)據(jù)；為低表示主設(shè)備忙。

二. AXI4_Lite

寫地址
signal	direction	中文理解
AWADDR	M2S	寫地址不支持burst傳輸
AWPROT	M2S	000 value recommended.詳情見AXI4
AWVALID	M2S	主設(shè)備給出的地址和相關(guān)控制信號有效
AWREADY	S2M	從設(shè)備已準備好接收地址和相關(guān)的控制信號
寫數(shù)據(jù)
WDATA	M2S	寫數(shù)據(jù)，近支持32bit位寬
WSTRB	M2S	寫字節(jié)選通信號，從設(shè)備可選擇忽略
WVALID	M2S	寫有效。為高指示數(shù)據(jù)有效。
WREADY	S2M	寫準備。為高表示從設(shè)備空閑，準備接收數(shù)據(jù)；為低表示從設(shè)備忙。
寫響應(yīng)
BRESP	S2M	EXOKAY狀態(tài)不支持
BVALID	S2M	寫響應(yīng)有效。為高指示響應(yīng)數(shù)據(jù)有效。
BREADY	M2S	寫響應(yīng)準備。為高表示主設(shè)備空閑，準備接收寫響應(yīng)；為低表示主設(shè)備忙。
讀地址
ARADDR	M2S	讀地址
ARPROT	M2S	000 value recommended.詳情見AXI4
ARVALID	M2S	讀地址有效信號。為高指示地址有效。
ARREADY	S2M	讀地址準備信號。為高表示從設(shè)備空閑，準備接收地址；為低表示從設(shè)備忙。
讀數(shù)據(jù)
RDATA	S2M	讀數(shù)據(jù)，指支持32bit位寬
RRESP	S2M	讀響應(yīng)，不支持EXOKAY
RVALID	S2M	讀有效。為高指示數(shù)據(jù)有效。
RREADY	M2S	讀準備。為高表示主設(shè)備空閑，準備接收數(shù)據(jù)；為低表示主設(shè)備忙。