? 學(xué)期快結(jié)束了，學(xué)了一個學(xué)期FPGA課程，通過自己思索加上老師的指導(dǎo)我完成了自己第一份交通燈的作業(yè)，我希望把經(jīng)驗分享給學(xué)習(xí)Verilog遇到困難的同學(xué)，更希望大家都能順利完成自己的作業(yè)。

??燈能左右改變方向，作品能夠模擬紅、黃、綠、左右轉(zhuǎn)彎燈等形式，按鍵可以操控?zé)舻臓顟B(tài)。并且，作品具備三個交通方式。例如雙閃緩行，應(yīng)急通道。

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做交通燈需要狀態(tài)機的知識

根據(jù)狀態(tài)機的輸出信號是否與電路的輸入有關(guān)分為 Mealy型狀態(tài)機和 Moore 型狀態(tài)機。

Mealy型狀態(tài)機：電路的輸出信號不僅與電路的當前的狀態(tài)有關(guān)，還與電路的輸入有關(guān)。

Moore型狀態(tài)機：電路的輸入僅與各觸發(fā)器的狀態(tài)有關(guān)，與電路的輸入無關(guān)。

? 一段式狀態(tài)機、二段式狀態(tài)機、三段式狀態(tài)機各自的特點

一段式狀態(tài)機: 僅適合非常簡單的狀態(tài)機設(shè)計，只涉及時序電路，消耗的邏輯比較少。

二段式狀態(tài)機：在組合邏輯特別復(fù)雜時適用，但要注意需在后面加一個觸發(fā)器以消除組合邏輯對輸出產(chǎn)生的毛刺。三段式?jīng)]有這個問題，由于第三個always會生成觸發(fā)器。

三段式狀態(tài)機：描述方法雖然代碼結(jié)構(gòu)復(fù)雜了一些，但是換來的優(yōu)勢是：使FSM做到了同步寄存器輸出，消除了組合邏輯輸出的不穩(wěn)定與毛刺的隱患，而且更利于時序路徑分組，一般來說在FPGA/CPLD等可編程邏輯器件上的綜合與布局布線效果更佳。

主程序如下

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?管腳約束如下：

create_clock?-period?10?[get_ports?clk_100m]
set_property?IOSTANDARD?LVCMOS33?[get_ports?{clk_100m}]
set_property?PACKAGE_PIN?P17?[get_ports?{clk_100m}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{rst_n}]
set_property?PACKAGE_PIN?P15?[get_ports?{rst_n}]

######################################################

set_property?IOSTANDARD?LVCMOS33?[get_ports?{sw[0]}]
set_property?PACKAGE_PIN?R1?[get_ports?{sw[0]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{sw[1]}]
set_property?PACKAGE_PIN?N4?[get_ports?{sw[1]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{sw[2]}]
set_property?PACKAGE_PIN?M4?[get_ports?{sw[2]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{sw[3]}]
set_property?PACKAGE_PIN?R2?[get_ports?{sw[3]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{sw[4]}]
set_property?PACKAGE_PIN?P2?[get_ports?{sw[4]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[0]}]
set_property?PACKAGE_PIN?K2?[get_ports?{led[0]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[1]}]
set_property?PACKAGE_PIN?J2?[get_ports?{led[1]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[2]}]
set_property?PACKAGE_PIN?J3?[get_ports?{led[2]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[3]}]
set_property?PACKAGE_PIN?H4?[get_ports?{led[3]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[4]}]
set_property?PACKAGE_PIN?J4?[get_ports?{led[4]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[5]}]
set_property?PACKAGE_PIN?G3?[get_ports?{led[5]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[6]}]
set_property?PACKAGE_PIN?G4?[get_ports?{led[6]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{led[7]}]
set_property?PACKAGE_PIN?F6?[get_ports?{led[7]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[0]}]
set_property?PACKAGE_PIN?D4?[get_ports?{seg[0]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[1]}]
set_property?PACKAGE_PIN?E3?[get_ports?{seg[1]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[2]}]
set_property?PACKAGE_PIN?D3?[get_ports?{seg[2]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[3]}]
set_property?PACKAGE_PIN?F4?[get_ports?{seg[3]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[4]}]
set_property?PACKAGE_PIN?F3?[get_ports?{seg[4]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[5]}]
set_property?PACKAGE_PIN?E2?[get_ports?{seg[5]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[6]}]
set_property?PACKAGE_PIN?D2?[get_ports?{seg[6]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{seg[7]}]
set_property?PACKAGE_PIN?H2?[get_ports?{seg[7]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{an[0]}]
set_property?PACKAGE_PIN?G6?[get_ports?{an[0]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{an[1]}]
set_property?PACKAGE_PIN?E1?[get_ports?{an[1]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{an[2]}]
set_property?PACKAGE_PIN?F1?[get_ports?{an[2]}]

set_property?IOSTANDARD?LVCMOS33?[get_ports?{an[3]}]
set_property?PACKAGE_PIN?G1?[get_ports?{an[3]}]
?文章來源地址http://www.zghlxwxcb.cn/news/detail-470628.html

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