本項(xiàng)目介紹如何用 Verilog 實(shí)現(xiàn)一個(gè)帶有預(yù)生成系數(shù)的簡(jiǎn)單 FIR 濾波器。
Things used in this project 、
Story
簡(jiǎn)陋的 FIR 濾波器是 FPGA 數(shù)字信號(hào)處理中最基本的構(gòu)建模塊之一，因此了解如何利用給定的抽頭數(shù)和相應(yīng)的系數(shù)值組裝一個(gè)基本模塊非常重要。因此，在這個(gè)關(guān)于在 FPGA 上入門 DSP 基礎(chǔ)知識(shí)的實(shí)用方法迷你系列中，我將從一個(gè)簡(jiǎn)單的 15 抽頭低通濾波器 FIR 開始，先在 Matlab 中生成初始系數(shù)值，然后將這些數(shù)值轉(zhuǎn)換為 Verilog 模塊中的使用值。
有限脈沖響應(yīng)或 FIR 濾波器的定義是，濾波器的脈沖響應(yīng)在一定時(shí)間內(nèi)趨于零值，因此它是有限的。脈沖響應(yīng)歸零所需的時(shí)間與濾波器的階（抽頭數(shù)）直接相關(guān)，而階（抽頭數(shù)）就是 FIR 底部傳遞函數(shù)多項(xiàng)式的階數(shù)。FIR 的傳遞函數(shù)不包含反饋，因此如果輸入一個(gè)值為 1 的脈沖，然后是一堆零值，那么輸出將只是濾波器的系數(shù)值。
任何濾波器的作用都是對(duì)信號(hào)進(jìn)行調(diào)節(jié)，主要側(cè)重于選擇濾除或允許哪些頻率通過。最簡(jiǎn)單的例子之一就是低通濾波器，它允許低于某一閾值（截止頻率）的頻率通過，同時(shí)大大衰減高于該閾值的頻率，如下圖所示。
本項(xiàng)目的主要重點(diǎn)是在 HDL（特別是 Verilog，但其概念可以很容易地轉(zhuǎn)換為 VHDL）中實(shí)現(xiàn) FIR，可將其分解為三個(gè)主要邏輯組件：將每個(gè)采樣時(shí)鐘送入的循環(huán)緩沖器，該緩沖器可適當(dāng)考慮串行輸入的延遲；每個(gè)抽頭系數(shù)值的乘法器；以及每個(gè)抽頭輸出相加結(jié)果的累加器寄存器。
由于我的重點(diǎn)是 FPGA 邏輯中的 FIR 機(jī)制，因此我只是使用 Simulink 和 Matlab 中的 FDA 工具為低通濾波器插入一些簡(jiǎn)單的參數(shù)，然后使用生成的系數(shù)值為 Verilog 模塊計(jì)算適當(dāng)?shù)募拇嫫髦担ㄉ院笸瓿桑?/p>
我選擇實(shí)施一個(gè)簡(jiǎn)單的 15 抽頭低通濾波器 FIR，采樣頻率為 1Ms/s，通帶頻率為 200 kHz，截止頻率為 355kHz，從而得到以下系數(shù)：
Create Design File for FIR Module
在新的 Vivado 項(xiàng)目中從頭開始，使用流程導(dǎo)航器窗口中的添加源選項(xiàng)為 FIR 模塊創(chuàng)建新的設(shè)計(jì)源。
在確定了 FIR 的階數(shù)（抽頭數(shù)）和系數(shù)值之后，下一組必須定義的參數(shù)是輸入采樣、輸出采樣和系數(shù)本身的位寬。
對(duì)于這個(gè) FIR，我選擇將輸入采樣和系數(shù)寄存器設(shè)置為 16 位寬，輸出采樣寄存器設(shè)置為 32 位寬，因?yàn)閮蓚€(gè) 16 位值的乘積是一個(gè) 32 位值（兩個(gè)值相乘的寬度相加得出乘積的寬度，因此如果我選擇 16 位輸入采樣和 8 位抽頭，那么輸出采樣的寬度將是 24 位）。
這些值也都是帶符號(hào)的，因此 MSB 被用作符號(hào)位，其余較低的位數(shù)則是值必須包含的位數(shù)（在選擇輸入采樣寄存器的初始寬度時(shí)務(wù)必牢記這一點(diǎn)）。要在 Verilog 中將這些值設(shè)置為有符號(hào)數(shù)據(jù)類型，需要使用關(guān)鍵字 signed：
reg signed [15:0] register_name;
接下來要解決的問題是如何在 Verilog 中處理系數(shù)值，需要將十進(jìn)制點(diǎn)值轉(zhuǎn)換為定點(diǎn)值。由于所有的系數(shù)值都小于 1，因此寄存器的全部 15 位（總共 16 位中的 MSB 為帶符號(hào)位）都可以用于小數(shù)位。通常，你必須決定寄存器中的整數(shù)部分和小數(shù)部分各占多少位。因此，轉(zhuǎn)換小數(shù)抽頭的數(shù)學(xué)方法是：（小數(shù)系數(shù)值）*(2^(15))，如果系數(shù)值為負(fù)數(shù)，該乘積的任何十進(jìn)制值都將被四舍五入，并計(jì)算該值的兩位數(shù)：
現(xiàn)在，我們終于可以專注于 FIR 模塊的邏輯了，首先是循環(huán)緩沖器，它引入串行輸入采樣流，并為濾波器的 15 個(gè)抽頭創(chuàng)建一個(gè)包含 15 個(gè)輸入采樣的數(shù)組。
always @ (posedge clk)
begin
if(enable_buff == 1'b1)
begin
buff0 <= in_sample;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
buff7 <= buff6;
buff8 <= buff7;
buff9 <= buff8;
buff10 <= buff9;
buff11 <= buff10;
buff12 <= buff11;
buff13 <= buff12;
buff14 <= buff13;
end
end
接下來，乘法階段將每個(gè)樣本乘以每個(gè)系數(shù)值：
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
acc0 <= tap0 * buff0;
acc1 <= tap1 * buff1;
acc2 <= tap2 * buff2;
acc3 <= tap3 * buff3;
acc4 <= tap4 * buff4;
acc5 <= tap5 * buff5;
acc6 <= tap6 * buff6;
acc7 <= tap7 * buff7;
acc8 <= tap8 * buff8;
acc9 <= tap9 * buff9;
acc10 <= tap10 * buff10;
acc11 <= tap11 * buff11;
acc12 <= tap12 * buff12;
acc13 <= tap13 * buff13;
acc14 <= tap14 * buff14;
end
end
乘法階段的結(jié)果值通過加法累積到寄存器中，最終成為濾波器的輸出數(shù)據(jù)流。
/* Accumulate stage of FIR */
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
m_axis_fir_tdata <= acc0 + acc1 + acc2 + acc3 + acc4 + acc5 + acc6 + acc7 + acc8 + acc9 + acc10 + acc11 + acc12 + acc13 + acc14;
end
end
最后，邏輯的最后一部分是 FIR 模塊的數(shù)據(jù)流接口。AXI 流接口是最常見的接口之一，因此我選擇了它來實(shí)現(xiàn)。其關(guān)鍵在于有效信號(hào)和就緒信號(hào)，這兩個(gè)信號(hào)可以控制上下游設(shè)備之間的數(shù)據(jù)流。這意味著 FIR 模塊需要向其下游設(shè)備提供一個(gè)有效信號(hào)，以表明其輸出為有效數(shù)據(jù)，同時(shí)在下游設(shè)備取消就緒信號(hào)時(shí)，能夠暫停（但仍保留）其輸出。FIR 模塊還必須能夠在其主站接口上以同樣的方式與上游設(shè)備進(jìn)行通信。
以下是 FIR 模塊的邏輯設(shè)計(jì)概覽：
請(qǐng)注意有效信號(hào)和就緒信號(hào)是如何設(shè)置 FIR 輸入循環(huán)緩沖器和乘法級(jí)的使能值的，以及數(shù)據(jù)或系數(shù)通過的每個(gè)寄存器是如何聲明為帶符號(hào)的。
FIR 模塊 Verilog 代碼：
`timescale 1ns / 1ps
module FIR(
input clk,
input reset,
input signed [15:0] s_axis_fir_tdata,
input [3:0] s_axis_fir_tkeep,
input s_axis_fir_tlast,
input s_axis_fir_tvalid,
input m_axis_fir_tready,
output reg m_axis_fir_tvalid,
output reg s_axis_fir_tready,
output reg m_axis_fir_tlast,
output reg [3:0] m_axis_fir_tkeep,
output reg signed [31:0] m_axis_fir_tdata
);
always @ (posedge clk)
begin
m_axis_fir_tkeep <= 4'hf;
end
always @ (posedge clk)
begin
if (s_axis_fir_tlast == 1'b1)
begin
m_axis_fir_tlast <= 1'b1;
end
else
begin
m_axis_fir_tlast <= 1'b0;
end
end
// 15-tap FIR
reg enable_fir, enable_buff;
reg [3:0] buff_cnt;
reg signed [15:0] in_sample;
reg signed [15:0] buff0, buff1, buff2, buff3, buff4, buff5, buff6, buff7, buff8, buff9, buff10, buff11, buff12, buff13, buff14;
wire signed [15:0] tap0, tap1, tap2, tap3, tap4, tap5, tap6, tap7, tap8, tap9, tap10, tap11, tap12, tap13, tap14;
reg signed [31:0] acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7, acc8, acc9, acc10, acc11, acc12, acc13, acc14;
/* Taps for LPF running @ 1MSps with a cutoff freq of 400kHz*/
assign tap0 = 16'hFC9C; // twos(-0.0265 * 32768) = 0xFC9C
assign tap1 = 16'h0000; // 0
assign tap2 = 16'h05A5; // 0.0441 * 32768 = 1445.0688 = 1445 = 0x05A5
assign tap3 = 16'h0000; // 0
assign tap4 = 16'hF40C; // twos(-0.0934 * 32768) = 0xF40C
assign tap5 = 16'h0000; // 0
assign tap6 = 16'h282D; // 0.3139 * 32768 = 10285.8752 = 10285 = 0x282D
assign tap7 = 16'h4000; // 0.5000 * 32768 = 16384 = 0x4000
assign tap8 = 16'h282D; // 0.3139 * 32768 = 10285.8752 = 10285 = 0x282D
assign tap9 = 16'h0000; // 0
assign tap10 = 16'hF40C; // twos(-0.0934 * 32768) = 0xF40C
assign tap11 = 16'h0000; // 0
assign tap12 = 16'h05A5; // 0.0441 * 32768 = 1445.0688 = 1445 = 0x05A5
assign tap13 = 16'h0000; // 0
assign tap14 = 16'hFC9C; // twos(-0.0265 * 32768) = 0xFC9C
/* This loop sets the tvalid flag on the output of the FIR high once
* the circular buffer has been filled with input samples for the
* first time after a reset condition. */
always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0) //if (reset == 1'b0 || tvalid_in == 1'b0)
begin
buff_cnt <= 4'd0;
enable_fir <= 1'b0;
in_sample <= 8'd0;
end
else if (m_axis_fir_tready == 1'b0 || s_axis_fir_tvalid == 1'b0)
begin
enable_fir <= 1'b0;
buff_cnt <= 4'd15;
in_sample <= in_sample;
end
else if (buff_cnt == 4'd15)
begin
buff_cnt <= 4'd0;
enable_fir <= 1'b1;
in_sample <= s_axis_fir_tdata;
end
else
begin
buff_cnt <= buff_cnt + 1;
in_sample <= s_axis_fir_tdata;
end
end
always @ (posedge clk)
begin
if(reset == 1'b0 || m_axis_fir_tready == 1'b0 || s_axis_fir_tvalid == 1'b0)
begin
s_axis_fir_tready <= 1'b0;
m_axis_fir_tvalid <= 1'b0;
enable_buff <= 1'b0;
end
else
begin
s_axis_fir_tready <= 1'b1;
m_axis_fir_tvalid <= 1'b1;
enable_buff <= 1'b1;
end
end
/* Circular buffer bring in a serial input sample stream that
* creates an array of 15 input samples for the 15 taps of the filter. */
always @ (posedge clk)
begin
if(enable_buff == 1'b1)
begin
buff0 <= in_sample;
buff1 <= buff0;
buff2 <= buff1;
buff3 <= buff2;
buff4 <= buff3;
buff5 <= buff4;
buff6 <= buff5;
buff7 <= buff6;
buff8 <= buff7;
buff9 <= buff8;
buff10 <= buff9;
buff11 <= buff10;
buff12 <= buff11;
buff13 <= buff12;
buff14 <= buff13;
end
else
begin
buff0 <= buff0;
buff1 <= buff1;
buff2 <= buff2;
buff3 <= buff3;
buff4 <= buff4;
buff5 <= buff5;
buff6 <= buff6;
buff7 <= buff7;
buff8 <= buff8;
buff9 <= buff9;
buff10 <= buff10;
buff11 <= buff11;
buff12 <= buff12;
buff13 <= buff13;
buff14 <= buff14;
end
end
/* Multiply stage of FIR */
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
acc0 <= tap0 * buff0;
acc1 <= tap1 * buff1;
acc2 <= tap2 * buff2;
acc3 <= tap3 * buff3;
acc4 <= tap4 * buff4;
acc5 <= tap5 * buff5;
acc6 <= tap6 * buff6;
acc7 <= tap7 * buff7;
acc8 <= tap8 * buff8;
acc9 <= tap9 * buff9;
acc10 <= tap10 * buff10;
acc11 <= tap11 * buff11;
acc12 <= tap12 * buff12;
acc13 <= tap13 * buff13;
acc14 <= tap14 * buff14;
end
end
/* Accumulate stage of FIR */
always @ (posedge clk)
begin
if (enable_fir == 1'b1)
begin
m_axis_fir_tdata <= acc0 + acc1 + acc2 + acc3 + acc4 + acc5 + acc6 + acc7 + acc8 + acc9 + acc10 + acc11 + acc12 + acc13 + acc14;
end
end
endmodule
Create a Simulation Source for its Testbench
要測(cè)試 FIR 模塊，需要?jiǎng)?chuàng)建一個(gè)測(cè)試平臺(tái)作為新的模擬源：
在 FIR 模塊中需要測(cè)試兩個(gè)主要部分：濾波器數(shù)學(xué)和 AXI 流接口。為此，我在測(cè)試臺(tái)中創(chuàng)建了一個(gè)狀態(tài)機(jī)，用于生成一個(gè)簡(jiǎn)單的 200kHz 正弦波，同時(shí)切換 FIR 接口從屬側(cè)的有效信號(hào)和主控側(cè)的就緒信號(hào)。
Testbench for FIR module:
`timescale 1ns / 1ps
module tb_FIR;
reg clk, reset, s_axis_fir_tvalid, m_axis_fir_tready;
reg signed [15:0] s_axis_fir_tdata;
wire m_axis_fir_tvalid;
wire [3:0] m_axis_fir_tkeep;
wire [31:0] m_axis_fir_tdata;
/*
* 100Mhz (10ns) clock
*/
always begin
clk = 1; #5;
clk = 0; #5;
end
always begin
reset = 1; #20;
reset = 0; #50;
reset = 1; #1000000;
end
always begin
s_axis_fir_tvalid = 0; #100;
s_axis_fir_tvalid = 1; #1000;
s_axis_fir_tvalid = 0; #50;
s_axis_fir_tvalid = 1; #998920;
end
always begin
m_axis_fir_tready = 1; #1500;
m_axis_fir_tready = 0; #100;
m_axis_fir_tready = 1; #998400;
end
/* Instantiate FIR module to test. */
FIR FIR_i(
.clk(clk),
.reset(reset),
.s_axis_fir_tdata(s_axis_fir_tdata),
.s_axis_fir_tkeep(s_axis_fir_tkeep),
.s_axis_fir_tlast(s_axis_fir_tlast),
.s_axis_fir_tvalid(s_axis_fir_tvalid),
.m_axis_fir_tready(m_axis_fir_tready),
.m_axis_fir_tvalid(m_axis_fir_tvalid),
.s_axis_fir_tready(s_axis_fir_tready),
.m_axis_fir_tlast(m_axis_fir_tlast),
.m_axis_fir_tkeep(m_axis_fir_tkeep),
.m_axis_fir_tdata(m_axis_fir_tdata));
reg [4:0] state_reg;
reg [3:0] cntr;
parameter wvfm_period = 4'd4;
parameter init = 5'd0;
parameter sendSample0 = 5'd1;
parameter sendSample1 = 5'd2;
parameter sendSample2 = 5'd3;
parameter sendSample3 = 5'd4;
parameter sendSample4 = 5'd5;
parameter sendSample5 = 5'd6;
parameter sendSample6 = 5'd7;
parameter sendSample7 = 5'd8;
/* This state machine generates a 200kHz sinusoid. */
always @ (posedge clk or posedge reset)
begin
if (reset == 1'b0)
begin
cntr <= 4'd0;
s_axis_fir_tdata <= 16'd0;
state_reg <= init;
end
else
begin
case (state_reg)
init : //0
begin
cntr <= 4'd0;
s_axis_fir_tdata <= 16'h0000;
state_reg <= sendSample0;
end
sendSample0 : //1
begin
s_axis_fir_tdata <= 16'h0000;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample1;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample0;
end
end
sendSample1 : //2
begin
s_axis_fir_tdata <= 16'h5A7E;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample2;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample1;
end
end
sendSample2 : //3
begin
s_axis_fir_tdata <= 16'h7FFF;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample3;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample2;
end
end
sendSample3 : //4
begin
s_axis_fir_tdata <= 16'h5A7E;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample4;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample3;
end
end
sendSample4 : //5
begin
s_axis_fir_tdata <= 16'h0000;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample5;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample4;
end
end
sendSample5 : //6
begin
s_axis_fir_tdata <= 16'hA582;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample6;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample5;
end
end
sendSample6 : //6
begin
s_axis_fir_tdata <= 16'h8000;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample7;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample6;
end
end
sendSample7 : //6
begin
s_axis_fir_tdata <= 16'hA582;
if (cntr == wvfm_period)
begin
cntr <= 4'd0;
state_reg <= sendSample0;
end
else
begin
cntr <= cntr + 1;
state_reg <= sendSample7;
end
end
endcase
end
end
endmodule
在 "source "窗口的模擬來源下，右擊測(cè)試平臺(tái)模塊并選擇 “Set as Top”，將其設(shè)置為頂層文件。
文章來源：http://www.zghlxwxcb.cn/news/detail-840952.html
Run a Behavioral Simulation
安裝好 FIR 模塊及其測(cè)試平臺(tái)后，從 Flow Navigator 窗口啟動(dòng) Vivado 中的仿真器，選擇 Run Behavioral Simulation（運(yùn)行行為仿真）選項(xiàng)（如果沒有綜合或?qū)崿F(xiàn)結(jié)果，這是唯一可用的選項(xiàng)）。
正如行為仿真所顯示的那樣，F(xiàn)IR 正在對(duì)信號(hào)進(jìn)行正確的濾波，并對(duì) AXI 流信號(hào)做出正確的響應(yīng)。
許多人可能會(huì)注意到，在使用這種特定 FIR 模塊的設(shè)計(jì)上運(yùn)行綜合和實(shí)現(xiàn)，會(huì)導(dǎo)致設(shè)計(jì)無法滿足時(shí)序要求（我相信閱讀此文的經(jīng)驗(yàn)豐富的 FPGA 工程師只需查看一下 FIR 模塊的 Verilog 就能知道這一點(diǎn)）。這將在 FPGA DSP 系列的下一篇文章中討論，因?yàn)樗鼮槲覀兲峁┝撕芎玫囊娊猓屛覀兞私庠跓o法滿足設(shè)置時(shí)序要求時(shí)如何重新思考設(shè)計(jì)。文章來源地址http://www.zghlxwxcb.cn/news/detail-840952.html
到了這里，關(guān)于FPGA 的 DSP：Verilog 中的簡(jiǎn)單 FIR 濾波器的文章就介紹完了。如果您還想了解更多內(nèi)容，請(qǐng)?jiān)谟疑辖撬阉鱐OY模板網(wǎng)以前的文章或繼續(xù)瀏覽下面的相關(guān)文章，希望大家以后多多支持TOY模板網(wǎng)！
