一、設(shè)計(jì)要求
當(dāng)設(shè)計(jì)文件加載到目標(biāo)器件后，撥動開關(guān)的K1，使其置為高電平，從輸入輸出觀測模塊的輸入端輸入一個頻率大于1Hz的時鐘信號，這時在數(shù)碼管上顯示這個時鐘信號的頻率值。如果使撥動開關(guān)置為低電平，數(shù)碼管上顯示的值為系統(tǒng)上的數(shù)字信號源的時鐘頻率。改變數(shù)字信號源的時鐘，看顯示的值是否與標(biāo)值一致（數(shù)碼管顯示2s刷新一次）。
二、設(shè)計(jì)原理
測頻實(shí)現(xiàn)框圖如下圖所示
所以我們可以通過設(shè)計(jì)六個模塊，最終在一個原理圖文件中連接，實(shí)現(xiàn)測頻
| 文件名稱 | 完成功能 |
|---|---|
| CLKOUT.VHD | 產(chǎn)生1Hz的閘門信號和1KHz的顯示掃描信號 |
| MUX.VHD | 被測信號源選擇模塊 |
| TELTCL.VHD | 在時鐘的作用下生成測頻的控制信號 |
| CNT10.VHD | 十進(jìn)制計(jì)數(shù)器，在設(shè)計(jì)中使用8個來進(jìn)行計(jì)數(shù) |
| SEG32B.VHD | 32位的鎖存器，在鎖存器控制信號的作用下，將計(jì)數(shù)的值鎖存 |
| DISPLAY.VHD | 顯示譯碼，將鎖存的數(shù)據(jù)顯示出來 |
控制信號時序關(guān)系如下圖所示
三、代碼實(shí)現(xiàn)
1.CLKOUT.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLKOUT IS
PORT(CLK:IN STD_LOGIC;
CLKOUT1:OUT STD_LOGIC;
CLKOUT1K:OUT STD_LOGIC);
END CLKOUT;
ARCHITECTURE BHV OF CLKOUT IS
BEGIN
PROCESS(CLK)
VARIABLE COUNT1:STD_LOGIC_VECTOR(25 DOWNTO 0);
VARIABLE COUNT2:STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE Q1:STD_LOGIC;
VARIABLE Q2:STD_LOGIC;
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
COUNT1:=COUNT1+1; --分頻計(jì)數(shù)器1
COUNT2:=COUNT2+1; --分頻計(jì)數(shù)器2
--這部分將50MHz頻率分頻得到1Hz方波
IF COUNT1="01011111010111100001000000" THEN --0.5s
--仿真時可以改成這條，因?yàn)殡娔X屏幕顯示有限"00000000000000000000000010"
Q1:='1';
ELSIF COUNT1="10111110101111000010000000" THEN --1s
--仿真時可以改成這條，因?yàn)殡娔X屏幕顯示有限"00000000000000000000000100"
Q1:='0';
COUNT1:="00000000000000000000000000";
END IF;
--這部分將50MHz頻率分頻得到1kHz方波
IF COUNT2="0110000110101000" THEN --0.5ms
--同上"0000000000000001"
Q2:='1';
ELSIF COUNT2="110000110101000" THEN --1.0ms
--同上"0000000000000010"
Q2:='0';
COUNT2:="0000000000000000";
END IF;
CLKOUT1 <=Q1; --輸出1Hz方波
CLKOUT1K<=Q2; --輸出1kHz方波
END IF;
END PROCESS;
END BHV;
仿真結(jié)果如下圖所示
通過修改分頻計(jì)數(shù)器的值可以得到不同頻率的方波
2.MUX.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MUX IS
PORT( SEL:IN STD_LOGIC;
CLKIN1:IN STD_LOGIC;
CLKIN2:IN STD_LOGIC;
CLKOUT:OUT STD_LOGIC);
END MUX;
ARCHITECTURE BHV OF MUX IS
BEGIN
PROCESS(SEL,CLKIN1,CLKIN2)
VARIABLE FLAG:STD_LOGIC;
BEGIN
IF SEL = '1'THEN
FLAG := '1';
ELSIF SEL = '0'THEN
FLAG := '0';
END IF;
IF FLAG = '1' THEN --當(dāng)開關(guān)撥動置1時
CLKOUT<=CLKIN1; --輸出波形1
ELSIF FLAG = '0' THEN --當(dāng)開關(guān)撥動置1時
CLKOUT<=CLKIN2; --輸出波形2
END IF;
END PROCESS;
END BHV;
仿真結(jié)果仿真結(jié)果如下圖所示
開關(guān)置1時，輸出CLKIN1的波形，開關(guān)置0時，輸出CLKIN2的波形
3.TELTCL.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TELTCL IS
PORT(CLK:IN STD_LOGIC;
EN:OUT STD_LOGIC;
CLR:OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
LOAD:OUT STD_LOGIC);
END TELTCL;
ARCHITECTURE BHV OF TELTCL IS
BEGIN
PROCESS(CLK)
VARIABLE T1:STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE T2:STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE TT:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE CEN:STD_LOGIC;
VARIABLE CCLR:STD_LOGIC;
VARIABLE CLOAD:STD_LOGIC;
BEGIN
IF CLK'EVENT AND CLK = '0' THEN
T1 := T1+1;
ELSIF CLK'EVENT AND CLK = '1' THEN
T2 := T2+1;
END IF;
--允許計(jì)數(shù)控制信號
IF (T1 = "01") OR (T1 = "11") THEN
CEN:='1';
ELSIF (T1 = "00") OR (T1 = "10") THEN
CEN:='0';
END IF;
--清零控制信號
TT := T1&T2;
IF TT = ("0001" OR "1011") THEN --"0000" "1010"
CCLR := '1';
ELSE
CCLR := '0';
END IF;
--鎖存控制信號
IF CEN = '1' THEN
CLOAD := '0';
ELSIF CEN = '0' THEN
CLOAD := '1';
END IF;
--最終賦值輸出
EN<=CEN;
CLR<=CCLR;
LOAD<=CLOAD;
Q<=TT;
END PROCESS;
END BHV;
仿真結(jié)果仿真結(jié)果如下圖所示
完美波形
4.CNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(CLK:IN STD_LOGIC;
EN:IN STD_LOGIC;
CLR:IN STD_LOGIC;
LOAD:OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CNT10;
ARCHITECTURE BHV OF CNT10 IS
BEGIN
PROCESS(CLK,EN,CLK)
VARIABLE COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE CLOAD:STD_LOGIC;
BEGIN
IF EN = '1' THEN
IF CLK'EVENT AND CLK = '1'THEN
COUNT := COUNT + 1; --每個時鐘上升沿計(jì)數(shù)器+1
IF COUNT = "1010" THEN --當(dāng)計(jì)數(shù)器值為10時清零
COUNT := "0000";
CLOAD := '1'; --LOAD輸出一個高電平
ELSE
CLOAD := '0';
END IF;
IF CLR = '1' THEN --當(dāng)清零控制信號為高電平時清零
COUNT := "0000";
END IF;
END IF;
LOAD <= CLOAD;
Q <= COUNT;
END IF;
END PROCESS;
END BHV;
仿真結(jié)果如圖所示
5.SEG32B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SEG32B IS
PORT(CLK:IN STD_LOGIC;
H1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H3:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H5:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H6:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H7:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
H8:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
X:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END SEG32B;
ARCHITECTURE BHV OF SEG32B IS
BEGIN
PROCESS(CLK)
VARIABLE T1:STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE T2:STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE TT:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE CX:STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
--因?yàn)槲覀冃枰唠娖竭@一段，所以需要判斷上升沿和下降沿
IF CLK'EVENT AND CLK = '0' THEN
T1 := T1+1;
ELSIF CLK'EVENT AND CLK = '1' THEN
T2 := T2+1;
END IF;
TT := T1&T2;
--判斷是否是高電平期間
IF TT = ("0001" OR "1011" OR "0000" OR "1010") THEN
CX:=CX; --高電平鎖存
ELSE
CX:=H8&H7&H6&H5&H4&H3&H2&H1; --低電平獲取輸入值
END IF;
X <= CX;
END PROCESS;
END BHV;
仿真結(jié)果如圖所示
高電平期間鎖存，低電平期間獲取值
6.DISPLAY.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY IS
PORT(CLK:IN STD_LOGIC;
P:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
SEGS7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END DISPLAY;
ARCHITECTURE BHV OF DISPLAY IS
BEGIN
PROCESS(CLK)
VARIABLE QT:STD_LOGIC_VECTOR(31 DOWNTO 0);
VARIABLE Q1:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q2:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q3:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q4:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q5:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q6:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q7:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE Q8:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE K:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
COUNT := COUNT + 1;
QT:=P;
Q8:=QT(31 DOWNTO 28);Q7:=QT(27 DOWNTO 24);
Q6:=QT(23 DOWNTO 20);Q5:=QT(19 DOWNTO 16);
Q4:=QT(15 DOWNTO 12);Q3:=QT(11 DOWNTO 8);
Q2:=QT(7 DOWNTO 4);Q1:=QT(3 DOWNTO 0);
SEL <= COUNT;
CASE COUNT IS
WHEN "000" => K := Q8;
WHEN "001" => K := Q7;
WHEN "010" => K := Q6;
WHEN "011" => K := Q5;
WHEN "100" => K := Q4;
WHEN "101" => K := Q3;
WHEN "110" => K := Q2;
WHEN "111" => K := Q1;
WHEN OTHERS =>NULL;
END CASE;
CASE K IS
WHEN "0000" =>SEGS7 <= "00111111"; --0
WHEN "0001" =>SEGS7 <= "00000110"; --1
WHEN "0010" =>SEGS7 <= "01011011"; --2
WHEN "0011" =>SEGS7 <= "01001111"; --3
WHEN "0100" =>SEGS7 <= "01100110"; --4
WHEN "0101" =>SEGS7 <= "01101101"; --5
WHEN "0110" =>SEGS7 <= "01111101"; --6
WHEN "0111" =>SEGS7 <= "00000111"; --7
WHEN "1000" =>SEGS7 <= "01111111"; --8
WHEN "1001" =>SEGS7 <= "01101111"; --9
WHEN "1010" =>SEGS7 <= "01110111"; --A
WHEN "1011" =>SEGS7 <= "01111100"; --B
WHEN "1100" =>SEGS7 <= "00111001"; --C
WHEN "1101" =>SEGS7 <= "01011110"; --D
WHEN "1110" =>SEGS7 <= "01111001"; --E
WHEN "1111" =>SEGS7 <= "01110001"; --F
WHEN OTHERS => SEGS7 <= "00000000";
END CASE;
END IF;
END PROCESS;
END BHV;
仿真結(jié)果如圖所示
數(shù)碼管位選循環(huán)點(diǎn)亮八個數(shù)碼管，達(dá)到視覺暫留，相當(dāng)于八個數(shù)碼管同時顯示；文章來源：http://www.zghlxwxcb.cn/news/detail-781548.html
四、綜合與仿真結(jié)果
參照教程完成六個VHD文件的轉(zhuǎn)換成模塊符號文件再將各個模塊按下圖所示方式連接
編譯后沒有錯誤即可，新建仿真頁，參數(shù)仿照下圖設(shè)置
開始仿真
由于條件有限，沒有設(shè)備進(jìn)行調(diào)試，所以仿真設(shè)置的分頻計(jì)數(shù)器較小。這里只要數(shù)碼管能正常顯示和移位即表明程序?qū)嶒?yàn)成功，若燒錄與FPAG芯片中些許問題可以對某些數(shù)據(jù)調(diào)參，以達(dá)到最優(yōu)效果。如果還有其他問題歡迎私聊我。文章來源地址http://www.zghlxwxcb.cn/news/detail-781548.html
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