項(xiàng)目場(chǎng)景:
Vivado版本: 2018.3
FPGA開(kāi)發(fā)板:XC7VX690T-2FFG1157I
背景:使用差分時(shí)鐘檢測(cè)基本電路觀察閃燈效果
報(bào)錯(cuò)如下
[Place 30-99] Placer failed with error: ‘IO Clock Placer failed’ Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
問(wèn)題描述
1.先分配完差分對(duì)IP核
2.在程序里面實(shí)例化IP核
clk_wiz_0 clk32M_inst
(// Clock in ports
// Clock out ports
.clk_out1(my_clk),
// Status and control signals
.locked(clk32Mpll_lock),
.clk_in1_p(clk32M_p),
.clk_in1_n(clk32M_n)
);
3.分配引腳
點(diǎn)擊Ctrl+S保存。
4.生成bit文件
此時(shí)提示有錯(cuò)誤。[Place 30-99] Placer failed with error: ‘IO Clock Placer failed’ Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
原因分析:
Vivado 認(rèn)為頂層模塊的clk時(shí)鐘引腳必須綁定板子特定的時(shí)鐘引腳,也就是我的差分對(duì)引腳綁定錯(cuò)了。又看了一遍原理圖確定是差分對(duì)引腳分配錯(cuò)誤,還有就是Vivado 差分對(duì) 只分配P管腳就行,N管腳自動(dòng)匹配。
解決方案:
更改管腳之后,生產(chǎn)Bit文件成功,燒錄到板子里面運(yùn)行效果與設(shè)計(jì)一致。文章來(lái)源:http://www.zghlxwxcb.cn/news/detail-505341.html
文章來(lái)源地址http://www.zghlxwxcb.cn/news/detail-505341.html
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