實(shí)驗(yàn)要求：
????????
（一）實(shí)驗(yàn)?zāi)康?/strong>
（1）掌握組合邏輯電路和時(shí)序電路的?FPGA實(shí)現(xiàn)方法；
（2）熟悉EDA開(kāi)發(fā)板和開(kāi)發(fā)軟件的使用方法；
（3）學(xué)習(xí)靜態(tài)數(shù)碼管的使用和7段數(shù)碼顯示譯碼器設(shè)計(jì)；
（4）掌握時(shí)鐘在時(shí)序電路中的作用；
（5）掌握分頻電路的實(shí)現(xiàn)方法。
（二）實(shí)驗(yàn)要求
設(shè)計(jì)BCD計(jì)數(shù)器，可任選模的大?。ㄗ畲竽Ｖ抵辽?位），實(shí)驗(yàn)要求：
（1）計(jì)數(shù)結(jié)果用3位數(shù)碼管顯示，顯示BCD碼；
（2）給出此項(xiàng)設(shè)計(jì)的仿真波形；
（3）選擇實(shí)驗(yàn)電路驗(yàn)證此計(jì)數(shù)器的功能。
（4）設(shè)計(jì)模值可變的輸入端口，通過(guò)輸入模值和設(shè)置信號(hào)改變計(jì)數(shù)器模值
（5）設(shè)置涉及1個(gè)開(kāi)關(guān)和一個(gè)按鍵，開(kāi)關(guān)作為使能控制，按鍵作為異步清0。（6）帶有進(jìn)位輸出，并進(jìn)位輸出用LED燈顯示
????????波形仿真應(yīng)能觀察到復(fù)位、使能、模值進(jìn)位輸出、設(shè)置模值。
????????在實(shí)驗(yàn)室用開(kāi)發(fā)板下載測(cè)試，下載測(cè)試現(xiàn)象與仿真相吻合。
????????按鍵能復(fù)位，使能無(wú)效時(shí)計(jì)數(shù)暫停，能切換模值。
????????為縮短仿真時(shí)間，仿真和下載測(cè)試時(shí)對(duì)50MHz系統(tǒng)時(shí)鐘的分頻系數(shù)可不同。
使用vivado軟件
可實(shí)現(xiàn)0-1024任意模
代碼如下文章來(lái)源：http://www.zghlxwxcb.cn/news/detail-449948.html
//源文件
module CNT(
input CLK, // 時(shí)鐘輸入
input SW1, // 開(kāi)關(guān)輸入，用于計(jì)數(shù)器使能控制
input KEY1, // 按鍵輸入，用于計(jì)數(shù)器異步清零
input [9:0] M_SET, // 模數(shù)設(shè)置輸入
output reg [9:0] cnt_count,
output reg [10:0] display_segout,
output reg LED_OUT //輸出，用于顯示進(jìn)位狀態(tài)
);
reg [6:0] BCD_OUT0; // BCD計(jì)數(shù)結(jié)果輸出
reg [6:0] BCD_OUT1; // BCD計(jì)數(shù)結(jié)果輸出
reg [6:0] BCD_OUT2; // BCD計(jì)數(shù)結(jié)果輸出
wire [9:0] M; // 計(jì)數(shù)器模數(shù)
wire [3:0] bw;
wire [3:0] sw;
wire [3:0] gw;
assign M[0]=M_SET[0];
assign M[1]=M_SET[1];
assign M[2]=M_SET[2];
assign M[3]=M_SET[3];
assign M[4]=M_SET[4];
assign M[5]=M_SET[5];
assign M[6]=M_SET[6];
assign M[7]=M_SET[7];
assign M[8]=M_SET[8];
assign M[9]=M_SET[9];
reg [19:0]count=0;
reg [30:0]count2=0;
reg [2:0] sel=0;
parameter T1MS=50000;
//多位數(shù)碼管顯示
always@(posedge CLK)
begin
count<=count+1;
if(count==T1MS)
begin
count<=0;
sel<=sel+1;
if(sel==3)
sel<=0;
end
end
仿真
//wire clk1;
//assign clk1=CLK;
//板子計(jì)數(shù)頻率
reg clk1;
always @(posedge CLK)
begin count2=count2+1;
if(count2/10000000%2==1) begin clk1=1'b1; count2=0;end
else clk1=1'b0;
end
板子數(shù)碼管顯示
always@(posedge CLK)
begin
case(sel)
0:display_segout<={4'b0111,BCD_OUT0};
1:display_segout<={4'b1011,BCD_OUT1};
2:display_segout<={4'b1101,BCD_OUT2};
default:display_segout<=11'b1111_1111111;
endcase
end
//計(jì)數(shù)器邏輯
always @(negedge clk1 or posedge KEY1)
begin
if(KEY1 == 1'b0) // 異步清零
cnt_count <= 10'd0;
else if(SW1 == 1'b1) // 使能控制
begin
if(cnt_count<M)
begin
cnt_count<=cnt_count+10'd1;
LED_OUT<=1'b0;
end
else
begin
cnt_count<=10'd0;
LED_OUT<=1'b1;
end
end
end
assign bw =cnt_count/100;
assign sw =cnt_count%100/10;
assign gw =cnt_count%10;
always @(posedge clk1 or negedge KEY1)
begin
if(!KEY1)
begin
BCD_OUT0<=7'b0000001;
BCD_OUT1<=7'b0000001;
BCD_OUT2<=7'b0000001;
end
else
begin
case (gw)
0:BCD_OUT0<=7'b0000001; 1:BCD_OUT0<=7'b1001111;
2:BCD_OUT0<=7'b0010010; 3:BCD_OUT0<=7'b0000110;
4:BCD_OUT0<=7'b1001100; 5:BCD_OUT0<=7'b0100100;
6:BCD_OUT0<=7'b0100000; 7:BCD_OUT0<=7'b0001111;
8:BCD_OUT0<=7'b0000000; 9:BCD_OUT0<=7'b0000100;
default: BCD_OUT0<=7'b0000001;
endcase
case (sw)
0:BCD_OUT1<=7'b0000001; 1:BCD_OUT1<=7'b1001111;
2:BCD_OUT1<=7'b0010010; 3:BCD_OUT1<=7'b0000110;
4:BCD_OUT1<=7'b1001100; 5:BCD_OUT1<=7'b0100100;
6:BCD_OUT1<=7'b0100000; 7:BCD_OUT1<=7'b0001111;
8:BCD_OUT1<=7'b0000000; 9:BCD_OUT1<=7'b0000100;
default: BCD_OUT1<=7'b0000001;
endcase
case (bw)
0:BCD_OUT2<=7'b0000001; 1:BCD_OUT2<=7'b1001111;
2:BCD_OUT2<=7'b0010010; 3:BCD_OUT2<=7'b0000110;
4:BCD_OUT2<=7'b1001100; 5:BCD_OUT2<=7'b0100100;
6:BCD_OUT2<=7'b0100000; 7:BCD_OUT2<=7'b0001111;
8:BCD_OUT2<=7'b0000000; 9:BCD_OUT2<=7'b0000100;
default : BCD_OUT2<=7'b0000001;
endcase
end
end
endmodule
//仿真文件
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/03/16 21:54:56
// Design Name:
// Module Name: sim_CNT
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
`timescale 1ns/1ps
module sim_CNT();
reg SW1,KEY1;
reg [9:0]M_SET;
wire [9:0] cnt_count;
wire [10:0] display_segout;
wire LED_OUT;
reg clk1;
initial
begin
clk1= 1'b0;
SW1 = 1'b0;
#2 KEY1 = 1'b1;
M_SET =10'b0000001111;
#2 KEY1 = 1'b0;
#2 KEY1 = 1'b1; SW1 = 1'b1; //計(jì)數(shù)使能信號(hào)有效，且不復(fù)位
end
always
begin
#10 clk1 = ~clk1;
end
CNT uu1(clk1,SW1,KEY1,M_SET,cnt_count,display_segout,LED_OUT);
endmodule
前任栽樹(shù)，后人乘涼，希望你們不要簡(jiǎn)單的cv喔大家有什么問(wèn)題可以私聊我哦。文章來(lái)源地址http://www.zghlxwxcb.cn/news/detail-449948.html
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